Processes for forming a metal-insulator-metal capacitor in a copper dual damascene process in an integrated circuit, such as a complimentary metal oxide semiconductor structure, generally require etching a via through an intermetal dielectric layer to expose a copper top plate of the capacitor. Another via generally must be etched through the intermetal dielectric layer and through a capacitor dielectric layer to expose a copper bottom plate of the capacitor. In prior processes, the etching step to form the vias had to be carefully controlled to ensure that the etching of the via to the top plate did not break through the capacitor dielectric and into the bottom plate, thereby causing an electrical short between the top and bottom plates. To help prevent such etch-through, the top plate was made relatively thick, such as about 1000–1400 angstroms. However, thickening the capacitor top plate introduced difficulties in subsequent dual damascene process steps for forming conductor trenches.
What is needed, therefore, is a process for forming metal-insulator-metal capacitor structures wherein timing constraints on via etch steps may be relaxed, while at the same time minimizing the thickness of the top capacitor plate to simplify the dual damascene trench-formation processes.